1. Field of the Invention
The present invention relates to a method for production of a silicon-on-insulator (SOI) transistor device.
More specifically, it relates to a wafer bonding method. The present invention may be used for bonding two substrates to form a clad substrate. For example, it may be utilized for bonding two semiconductor wafers to form a composite semiconductor wafer.
An SOI structure is useful for semiconductor devices and other electronic components. In this technique, a silicon portion is placed on an insulator portion and various semiconductor elements are fabricated in the silicon portion. As one means for formation of an SOI structure, there is known the technique of bonding a separate substrate to a silicon substrate having insulator layer on the surface with the insulator and then polishing the silicon substrate to form silicon portions on the insulator layer. This is generally called a bonding SOI (for the bonding technique, see for example Nikkei McGraw-Hill "Nikkei Microdevices", March 1988, p 84)
Further, the present invention relates to a SOI transistor device, in particular a semiconductor device having capacitor storage nodes buried in a thin film semiconductor layer using the SOI structure.
2. Description of the Related Art
The SOI structure is used for various applications. For example, by forming elements in the semiconductor portion on the insulator material, a semiconductor device with good element isolation can be obtained from the beginning.
Art example of the SOI structure to which the present invention is applied will be explained below.
Numerous proposals have been made regarding SOI structure semiconductor devices. There are also numerous means for formation of the same. When applying the present invention, any of these may be used. One method of formation is to form a so-called bonding SOI structure. The formation of an SOI structure will be explained referring to FIGS. 1A to 1E taking as an example this technique (see Extended Abstracts on the 21st Conference on Solid State Devices and Materials, Tokyo, 1989, pp. 89-92, M. Hashimoto et. al., "Low Leakage SOI MOSFETs Fabricated Using a Wafer Bonding Method".)
As shown in FIG. 1A, one surface of a silicon substrate 1 (in general, use is made of a silicon wafer with a high degree of flatness, referred to here as the "substrate A") is patterned by photolithography or etching to form depressions of a depth of 1500 angstroms or less. Next, an SiO.sub.2 film is formed on this surface by chemical vapor deposition (CVD) etc. so as to form an insulator 2, thereby obtaining a structure of a silicon substrate 1 with an insulator 2 on one side. The insulator 2 is formed as an uneven film as illustrated due to the topography of the patterned silicon substrate 1. Further, a polycrystalline silicon film etc. is formed as a bonding layer 3 on the insulator 2 by CVD etc. to a thickness of about 5 .mu.m. The result is the structure of FIG. 1A. The polycrystalline silicon film forming the bonding layer 3 is used for formation of a highly smooth bonding surface when bonding another substrate (the substrate 4 shown by "B" in FIG. 1C) in a later step.
Next, the surface of the bonding layer 3 is polished to flatten it and obtain a highly smooth surface (FIG. 1B). By this, the bonding layer 3 (polycrystalline silicon film) is reduced to a thickness of 3 .mu.m or less.
Another substrate 4 (referred to here as the "substrate B") is placed in close contact with the polished surface of the bonding layer 3. The two surfaces are bonded by pressing them closely together. As a result the bonded structure shown in FIG. 1C is obtained. In general, it is said that a firm bond is achieved by the hydrogen bonding caused by the action of water or hydroxyl groups interposed between the two surfaces. This assembly is usually then heated for heat bonding to form a strong bonding. The bonding strength is generally at least 200 kg/cm.sup.2 and sometimes as high as 2000 kg/cm.sup.2. As the other substrate(substrate B) which is bonded use is usually made of the same type of silicon substrate as the substrate 1 (substrate A). This is because a heating step is often applied after the bonding so there is a danger of trouble if the heat expansion and other physical properties are not equal. If this were not a problem, then in the related art shown in FIG. 1, for example, the other substrate would function only as a support, so would not have to absolutely be a silicon substrate. However, if forming elements in the other substrate(substrate B) which is bonded the substrate would have to be a semiconductor substrate allowing the formation of elements.
Next, the substrate 1 is ground to reduce the silicon portion of the substrate 1 to a thickness of about 5 .mu.m or less to form a residual film and obtain the structure shown in FIG. 1D. FIG. 1C to FIG. 1E show the assembly turned upside down from FIG. 1A and FIG. 1B. This is because the assembly is turned upside down to put the substrate 1 at the top for grinding to obtain the structure shown in FIG. 1D and for the following selective polishing step.
Next, selective polishing is performed. Precision polishing is performed here until the insulator 2 is exposed. As a result, as shown in FIG. 1E, a structure is obtained with silicon portions 10 present on and surrounded by the insulator 2. The silicon portions 10 form the SOI film. In this structure with silicon portions 10 present in an insulator 2 (SOI structure), elements are fabricated in the silicon portions 10. As shown in FIG. 1E, the silicon portions 10 are surrounded by the insulator 2, so the elements are completely isolated from the very start.
FIGS. 1A to 1E showed the silicon portions 10 enlarged for clarifying the illustration. In actuality, there are a large number of fine silicon portions 10.
When forming the bonding SOI structure as described above, sometimes air bubbles are entrained in the bonding interface. Explaining this using FIG. 1C, when bonding the polycrystalline silicon film 3 surface on the substrate 1 with the substrate 4, air bubbles sometimes are entrained at the interface. This is because when bonding flat surfaces of the substrates, there are numerous points of contact and air bubbles easily are entrained. The air bubbles are of a size, for example, of about 0.5 .mu.m to 5 mm.
The bonding surfaces are not in close contact at the portions where the air bubbles are entrained so sufficient bonding is not achieved and peeling easily occurs. For example, after the grinding the surface of FIG. 1D, the thickness t.sub.1 of the film including the substrate 1 on the substrate 4 is 4 to 20 .mu.m, usually about 5 to 10 .mu.m or so, so if there are air bubbles present, peeling easily occurs. This sometimes becomes a source of contamination and can have a serious impact on the fabrication of the elements. For example, the wafers are sometimes scratched by the contamination during the polishing. The peeling due to the air bubbles forms contamination and impairs the reliability of the elements. In the state of FIG. 1E, the thickness t.sub.2 of the film on the silicon portion 10 side of the substrate is even thinner, about 3 to 4 .mu.m. If peeling occurs here, it becomes a source of contamination in the same way and sometimes ends up resulting in a defective element.
Therefore, it is necessary to ensure that no air bubbles format the bonding portion of the two substrates.
In the past, to prevent the formation of air bubbles between the two substrates to be bonded when forming a bonding SOI, as shown in FIG. 2A to 2C, the technique was employed of using a first support 13 for supporting one substrate 12 and a second support jig 14 for supporting another substrate 11, for example, a semiconductor wafer, using the second support jig 14 to make the surface of the supported substrate 11 convex, and bonding with the convexity facing the substrate 12 (the convexity is shown in an exaggerated manner to make the illustration clearer).
In the above type of technique, however, since one substrate 12 is made to be convex for bonding, there is some expansion and contraction of the pattern on the substrate 12, though slight. That is, when the bonding surface of the substrate 1s convex in shape, in the case of a substrate having a device pattern, the bonding is performed with elongation of the pattern due to the curvature of the convexity. Therefore, there is a possibility of misalignment of the pattern pitch and pattern deviation in the succeeding exposure step. Further, even if the second support jig 14 supporting the substrate 11 is comprised of, for example, a vacuum chuck, it does not necessarily mean that the substrate 11 can be supported with a good convexity. Further, when bonding the substrates to form a flat composite substrate, that is, when bonding the substrates from the state of FIG. 2B to the state of FIG. 2C, a good, tight bond is not achieved and therefore sometimes pattern elongation or contraction will end up occurring. As a result, with the above described bonding technique, where one of the substrates was made convex, it was difficult to keep up with the demands of the recent technique--where patterns are being increasingly miniaturized.
Next, the other problem related to prior SOI technique will be explained.
The element isolation pattern of an SOI structure obtained by the bonding method is formed, for example, by photolithography of the SOI wafer. There are problems in the photolithographic step, however. That is, in general, positioning marks known as alignment marks are formed at several locations on the chip so as to enable positioning during the photolithography step. Further, separate so-called "vernier" portions are generally formed at one position for each mark on the chip for the purpose of confirmation of the positioning. FIG. 3 and FIG. 4 illustrate the alignment marks in the case of positive photolithography. FIG. 4 shows the sectional shape of an alignment mark portion, while FIG. 3 shows the structure from a plane view. In FIG. 3, the case of positive photolithography is shown. The portion 21 in FIG. 3 is a SOI layer forming the semiconductor portion, while the portion 22 is the SiO.sub.2 forming the insulating material (note that in the case of negative photolithography, 21 designates conversely SiO.sub.2 and 22 designates the SOI layer). In FIG. 3, "O" indicates the center (origin) of the coordinate system.
FIG. 4 shows the sectional structure of the alignment mark in the case of making a gate window. In FIG. 4, 27 is the semiconductor portion (Si) in this example, while 24 is the insulator (SiO.sub.2) surrounding this semiconductor portion. Reference numeral 25 is a polycrystalline silicon layer, while 26 is a top layer of tungsten silicide etc. Here, the semiconductor portion 27 forming the SOI layer has a level difference of as much as 40 nm from the SiO.sub.2 portion of the insulating material 24 (see FIG. 4). When using this mark to form a resist pattern on a film with an extremely high reflectance, the exposure apparatus must be able to accurately detect a level difference of as little as 40 nm. This detection is extremely difficult in practice.
FIG. 5 shows the waveform of the alignment signal in the related art. As illustrated there, the signal-to-noise ratio (S/N) ratio is extremely small and the chance of picking up a false signal is high. In FIG. 5, "O" shows the signal peaks.
Use is made of a vernier portion even when measuring the alignment after exposure visual detection of the vernier is difficult for the same reasons, however, so accurate measurement of the alignment is not possible.
Next, an explanation will be made of an example of a dynamic random access memory (DRAM) using an SOI structure according to the related art.
Along with the reduction in size of DRAM memory cells and their higher density, use has been made of the SOI structure to secure the required storage capacity. Development has been made of DRAMs and other semiconductor devices with capacitors buried under a semiconductor layer. The key portions of a DRAM or other semiconductor device using such an SOI structure is shown in FIGS. 6A and 6B.
As shown in FIGS. 6A and 6B (wherein FIG. 6A is a sectional view along the line A--A in FIG. 6B), in this semiconductor device, a semiconductor layer 32a constituted by silicon is formed on top of an insulating film layer 42 to produce an SOI structure. On the semiconductor layer 32a are laid word lines 36a and 36b over a gate insulating layer. On top of this are laid an interlayer insulating layer and bit lines 40. The bit lines 40 are connected to the semiconductor layer 32a or the semiconductor layer 32b through bit line contacts 39 made in the interlayer insulating layer. The word lines 36a and 36b serve also as gate electrodes. A channel portion 38 is formed at the semiconductor layer 32a or 32b positioned below the same. As a result, a DRAM memory cell transistor is formed at this portion.
Under the insulating film layer 42 is buried a capacitor storage node 44. The storage node 44 and the semiconductor layer 32a are connected through a contact 43 formed in the insulating film layer 42. Under the storage node 44 is laid a cell plate layer 48 through a capacitor insulating film layer 46. In this semiconductor device, the storage node 44, the insulating film layer 46, and the cell plate 48 constitute the capacitor.
In a semiconductor device of such a structure, the area occupied by the capacitor is made large to increase the capacity of the capacitor. Also, the level difference of the capacitor does not have a detrimental effect on the wiring patterning.
However, in a semiconductor device of an SOI structure now under development, as shown in FIG. 6A and 6B, the layout pattern of the storage node 44 is positioned at the layers below the channel portion 38 of the semiconductor layer 32a or 32b, so there were the following problems:
The potential of the storage node 44 changes from the ground level to the power source voltage depending on the state of the data held. If the storage node 44 is positioned directly under the channel portion 38, the changes in potential of the storage node 44 will affect the channel portion 38 and cause a change in its potential state and fluctuations in the threshold voltage. Therefore, it becomes difficult to maintain the optimal threshold voltage and there is a danger of a reduction of the writing voltage or a deterioration of the holding of the data.
Note that the layout pattern of the storage node shown is one for the layout of storage type capacitors employed for a 4M DRAM, 16M DRAM, etc.
Further, proposal has been made of a DRAM cell structure with a storage node buried under a thin film semiconductor layer using an SOI structure.
FIG. 7 is a schematic sectional view of a DRAM cell using an SOI structure according to the related art.
In this conventional DRAM cell using an SOI structure, as shown in FIG. 7, an insulating film layer 68 is laid under the thin film semiconductor layer 58. The insulating film layer 68 had contact holes 69 formed in it near the thin film semiconductor layer 58. Under the insulating film layer 68 were formed storage nodes 60. The capacitor storage nodes 60 were connected to the thin film semiconductor layer through the contact holes 69. Under the storage nodes 60 was laid a cell plate layer 66 through a capacitor insulating film 64. The capacitor storage nodes 60, insulating film layer 64, and cell plate layer 66 constituted capacitors. Note that in the figure, 54a and 54b are word lines and 56 is a bit line.
In such a structure of a DRAM cell, it is possible to generate more surface area of the side walls and obtain a desired storage capacity by increasing the height (depth) of the storage nodes 60. Further, since the pattern for formation of the storage nodes 60 is a pattern which removes overlapping margin of the contact holes 69, the area of the cells can be expected to be considerably reduced.
When making such a DRAM cell of the related art, however, as shown in FIG. 8, an insulating layer 68 is laid on the semiconductor substrate 67 for formation of the semiconductor layer 58 shown in FIG. 7, contact holes 69 are formed, a polycrystalline silicon film forming the storage nodes 60 is laid, then the polycrystalline film is etched by reactive ion etching (RIE) etc. to form the node formation holes 61 and the storage nodes 60 are formed. In the related art, however, due to the overetching at the time of etching for formation of the storage nodes, the polycrystalline silicon in the contact holes 69 and the surface of the thin film semiconductor substrate 67 were even etched and there was the danger of formation of the grooves A.
To achieve a higher density, if the pattern for formation of the storage nodes 60 is made a pattern for removing the overlapping margin of the contact holes 69, during the RIE overetching for formation of the storage nodes 60, part of the polycrystalline silicon film filled in the contact holes 69 is also exposed to the etching. As a result, the polycrystalline silicon is etched even in the contact holes 69. If the amount of overetching can be controlled so that the etching stops at the inside of the contact holes 69, there would be no problem, but if it reaches the surface of the substrate 67 and forms grooves "A" there, it creates defective shapes, leak deficiencies, etc. at the time of processing the substrate in later steps. In particular, the higher the height of the storage node 60 is made to secure the capacitor capacity, the greater the etching error becomes and the more difficult control of the overetching becomes and the easier defects are to occur. For example, recently, the thickness of the polycrystalline silicon film has to be at least about 2 .mu.m. If the etching precision in RIE etc. is 10 percent or so with respect to the thickness of the polycrystalline silicon film, when etching the polycrystalline silicon film to form a node formation hole 61, the etching error is at least .+-.200 nm. On the other hand, the thickness of the insulating film layer 68 is about 200 to 400 nm. In this way, the thickness of the insulating film layer 68 is not sufficiently great with respect to the etching error and there is a danger of formation of grooves A in the surface of the substrate 67.